Integrated circuit (IC) technology is continuously increasing in complexity due to improvements in semiconductor process fabrication techniques. Complete system-on-chip (SoC) solutions, involving many elements such as a processor, timer, interrupt controller, bus, memory, and/or embedded software on a single circuit, are now available for a variety of applications. Software development, early hardware architecture exploration and functional verification of a complex SoC or processor device are challenges faced by the semiconductor industry. At process fabrication technologies of 65 nm and smaller, with millions of transistors available to implement large and complex SoCs, the challenge of functionally verifying such complex devices grows exponentially. Industry data suggests that upwards of 80% of all project resources are allocated to software development and functional verification of these devices.
A typical design process begins with a software program that describes the behavior or functionality of a circuit to be created. Such a software program is typically written in procedural programming languages such as C/C++ that define behavior to be performed with limited implementation details. Register transfer level (RTL) is a level at which a digital system is described in terms of synchronous transfer between functional units. RTL is one level higher than a gate level. At RTL, every operation's order of execution (and thus timing) is completely specified. An RTL model of an IC device may be used as an input to an automated digital synthesis tool to create a gate level netlist. As used herein, the term “model” is used to describe a unit, which may be realized in software and embodied on a computer readable storage medium, that represents the behavior of a desired device (e.g., a system block) in a form other than the actual device. Logic synthesis tools convert an RTL description to a gate level netlist. A gate level netlist further goes through transistor level transformations by so-called place and route tools to reach the physical IC level.